Slang Netlist

Slang Netlist is a library and tool leveraging slang to analyse the source-level static connectivity of a System Verilog design and is intended to be a replacement for Netlist Paths (see below). Slang Netlist is included as a tool in the slang project.

• GitHub

Netlist Paths

Netlist Paths is a library and command-line tool for querying a Verilog netlist. It reads an XML representation of a design’s netlist, produced by Verilator, and provides facilities for inspecting types, variables and paths. The library is written in C++ and has a Python interface.

• GitHub
• Documentation

Hex processor

The Hex Architecture is a very simple processor designed by David May and intended for explaining how a computer works. This repository contains an implementation in Verilog and basic tooling written in C++ for developing programs (a compiler, assembler and simulator). It was written out of curiosity and to serve as an example of how high-level programs relate to the underlying hardware implementation.

• GitHub
• Documentation

PRNG testing

This repository contains facilities for comprehensively testing PRNGs using statistical test suites. It provides a facility to run a PRNG against TestU01, PractRand and Gjrand, with parallel runs from different seeds and permutations of the output bits, and a script for summarising results across all the runs. This testing methodology was used for the investigation in this paper.

• GitHub

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Older projects

• Three-channel, high-power LED driver,
  PCB design files and microcontroller code.
• Convolutional neural network from scratch,
  a simple C++ implementation of a convolutional neural network.
• Sire compiler v2,
  a rewrite of the original sire implementation in Python, and this time targeting the XMOS XS1 architecture via the XC language.
• Sire compiler v1,
  a first version of the sire language and runtime system for dynamic process creation, directly targeting the XMOS XS1 architecture.