Tag: verilog
Benchmarking Slang Netlist on open-source designs
Sep 2026
Measuring the runtime, memory use and thread scaling of Slang Netlist across the RTLMeter suite of open-source designs, and using it to find undriven inputs in a RISC-V core.
Silicon infrastructure
Aug 2023
Thoughts on the requirements of software infrastructure to support chip design.
Querying logical paths in a Verilog design
Nov 2018
A description of a command-line tool I created for tracing timing paths from a flattened netlist back through the RTL.
Writing synthesizable Verilog
May 2018
Coding style for RTL design using Verilog / SystemVerilog. Updated 2024.