Functions
and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a	b (crosses @c .)
and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c	top (no segment)</td ></tr >< tr >< td > @c top.**</td >< td > @c top
port connections(named and positional). - Interface modport ports and their connection expressions. - Continuous assignments(@c assign). - Procedural blocks dependencies through function arguments are not tracked Assertions and coverage constructs are ignored System tasks and	functions (@c $display, etc.) are ignored. - @c force/@c release and @c deassign are not modelled. - Dynamic types

Variables
and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments	Examples
and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top	a
and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td >< td > c topX</td ></tr >< tr >< td > c top leaf</td >< td > c top	leaf
and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td >< td > c topX</td ></tr >< tr >< td > c top leaf</td >< td > c top c top mid c top a b leaf</td >< td > c topXleaf</td ></tr >< tr >< td > c top u_</td >< td > c top	u_a
and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td >< td > c topX</td ></tr >< tr >< td > c top leaf</td >< td > c top c top mid c top a b leaf</td >< td > c topXleaf</td ></tr >< tr >< td > c top u_</td >< td > c top c top u_b</td >< td > c top	u_ab
and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td >< td > c topX</td ></tr >< tr >< td > c top leaf</td >< td > c top c top mid c top a b leaf</td >< td > c topXleaf</td ></tr >< tr >< td > c top u_</td >< td > c top c top u_b</td >< td > c top c top u_a x</td ></tr >< tr >< td > c **leaf</td >< td > c c mid c top mid leaf</td >< td > c xleaf</td ></tr ></table > subsection sv support SystemVerilog support The following SystemVerilog constructs are handled during netlist	construction
and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td >< td > c topX</td ></tr >< tr >< td > c top leaf</td >< td > c top c top mid c top a b leaf</td >< td > c topXleaf</td ></tr >< tr >< td > c top u_</td >< td > c top c top u_b</td >< td > c top c top u_a x</td ></tr >< tr >< td > c **leaf</td >< td > c c mid c top mid leaf</td >< td > c xleaf</td ></tr ></table > subsection sv support SystemVerilog support The following SystemVerilog constructs are handled during netlist including generate blocks and arrays of instances	Input
and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td >< td > c topX</td ></tr >< tr >< td > c top leaf</td >< td > c top c top mid c top a b leaf</td >< td > c topXleaf</td ></tr >< tr >< td > c top u_</td >< td > c top c top u_b</td >< td > c top c top u_a x</td ></tr >< tr >< td > c **leaf</td >< td > c c mid c top mid leaf</td >< td > c xleaf</td ></tr ></table > subsection sv support SystemVerilog support The following SystemVerilog constructs are handled during netlist including generate blocks and arrays of instances	output
and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td >< td > c topX</td ></tr >< tr >< td > c top leaf</td >< td > c top c top mid c top a b leaf</td >< td > c topXleaf</td ></tr >< tr >< td > c top u_</td >< td > c top c top u_b</td >< td > c top c top u_a x</td ></tr >< tr >< td > c **leaf</td >< td > c c mid c top mid leaf</td >< td > c xleaf</td ></tr ></table > subsection sv support SystemVerilog support The following SystemVerilog constructs are handled during netlist including generate blocks and arrays of instances and inout	ports
port connections(named and positional). - Interface modport ports and their connection expressions. - Continuous assignments(@c assign). - Procedural blocks dependencies through function arguments are not tracked Assertions and coverage constructs are ignored System tasks and	classes

Function Documentation

◆ b()

and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a b ( crosses @ c . )

◆ functions()

port connections(named and positional). - Interface modport ports and their connection expressions. - Continuous assignments( @c assign). - Procedural blocks dependencies through function arguments are not tracked Assertions and coverage constructs are ignored System tasks and functions	(	@c	$display,
		etc.	)

◆ top()

and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c top ( no segment )

Variable Documentation

◆ a

and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top a

◆ classes

port connections(named and positional). - Interface modport ports and their connection expressions. - Continuous assignments( @c assign). - Procedural blocks dependencies through function arguments are not tracked Assertions and coverage constructs are ignored System tasks and classes

◆ construction

and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td><td> c topX</td></tr><tr><td> c top leaf</td><td> c top c top mid c top a b leaf</td><td> c topXleaf</td></tr><tr><td> c top u_</td><td> c top c top u_b</td><td> c top c top u_a x</td></tr><tr><td> c** leaf</td><td> c c mid c top mid leaf</td><td> c xleaf</td></tr></table> subsection sv support SystemVerilog support The following SystemVerilog constructs are handled during netlist construction

◆ Examples

and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments Examples

◆ Input

and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td><td> c topX</td></tr><tr><td> c top leaf</td><td> c top c top mid c top a b leaf</td><td> c topXleaf</td></tr><tr><td> c top u_</td><td> c top c top u_b</td><td> c top c top u_a x</td></tr><tr><td> c** leaf</td><td> c c mid c top mid leaf</td><td> c xleaf</td></tr></table> subsection sv support SystemVerilog support The following SystemVerilog constructs are handled during netlist including generate blocks and arrays of instances Input

◆ leaf

and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td >< td > c topX</td ></tr >< tr >< td > c top leaf</td >< td > c top c top mid c top a b leaf</td >< td > c topXleaf</td ></tr >< tr >< td > c top u_</td >< td > c top c top u_b</td >< td > c top c top u_a x</td ></tr >< tr >< td > c **leaf</td >< td > c c mid leaf

◆ output

and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td><td> c topX</td></tr><tr><td> c top leaf</td><td> c top c top mid c top a b leaf</td><td> c topXleaf</td></tr><tr><td> c top u_</td><td> c top c top u_b</td><td> c top c top u_a x</td></tr><tr><td> c** leaf</td><td> c c mid c top mid leaf</td><td> c xleaf</td></tr></table> subsection sv support SystemVerilog support The following SystemVerilog constructs are handled during netlist including generate blocks and arrays of instances output

◆ ports

and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td><td> c topX</td></tr><tr><td> c top leaf</td><td> c top c top mid c top a b leaf</td><td> c topXleaf</td></tr><tr><td> c top u_</td><td> c top c top u_b</td><td> c top c top u_a x</td></tr><tr><td> c** leaf</td><td> c c mid c top mid leaf</td><td> c xleaf</td></tr></table> subsection sv support SystemVerilog support The following SystemVerilog constructs are handled during netlist including generate blocks and arrays of instances and inout ports

◆ u_a

and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td><td> c topX</td></tr><tr><td> c top leaf</td><td> c top c top mid c top a b leaf</td><td> c topXleaf</td></tr><tr><td> c top u_</td><td> c top u_a

◆ u_ab

and slang s LRM style c handling and lets the recursive wildcard stand in for zero or more intermediate path segments c top foo</td >< td > c top a c c top c top a b c</td><td> c topX</td></tr><tr><td> c top leaf</td><td> c top c top mid c top a b leaf</td><td> c topXleaf</td></tr><tr><td> c top u_</td><td> c top c top u_b</td><td> c top u_ab

Functions

Variables