Thoughts on the requirements of software infrastructure to support chip design.
A rationale and strawman for a processor to accelerate dynamic-language workloads.
A hardware implementation of a Hex processor with some basic tooling, including a complete compiler for a simple programming language.
A short summary of an investigation into the statisitical quality and implementation cost in hardware of the xoroshiro128aox PRNG.
Using Hamming Codes for single error correction and double error detection.
Details of new chips that have been built recently to accelerate machine intelligence workloads.
A description of how digital circuits are modified to allow scan testing to be performed.
A description of a command-line tool I created for tracing timing paths from a flattened netlist back through the RTL.
The rules for composing Vim’s motions and operators.
Coding style for RTL design using Verilog / SystemVerilog. Updated 2024.
Using empirical statistical tests to determine the quality of PRNGs.
A C++ implementation of a convoluational neural network building on the explanation in Michael Nielsen’s book ‘Neural Networks and Deep Learning’.
A review of state-of-the-art techniques used.
Neural networks have become a hot topic in computing and their development is progressing rapidly. They have a long history with some of the first …
An overview of the key features of the language, many of which derive from occam.
The XMP-64 is an experimental single-board distributed-memory parallel computer with 512 hardware threads and is programmable with a C-like language. It was developed by …
An overview of my PhD thesis.